Pixel level expandable memory array for voltage domain global shutter

Abstract

A sample and hold (SH) circuit includes a pixel level connection coupled to a pixel cell. A reset row transistor is coupled between a first supply voltage and the pixel level connection. A source follower row transistor having a gate is coupled to the pixel level connection. A row select row transistor is coupled between the source follower row transistor and a bitline. A first storage transistor is coupled to the pixel level connection. A first storage device is coupled between the first storage transistor and a second supply voltage. A second storage transistor is coupled to the pixel level connection. A second storage device is coupled between the second storage transistor and the second supply voltage.

Dependencies are inferred from the claim text.