Semiconductor device drive circuit

A semiconductor device drive circuit, comprising:

• a pulse generation circuit outputting an on-pulse signal synchronized with a leading edge of an input signal and an off-pulse signal synchronized with a falling edge;
• an on-side level shift circuit outputting a level shift on-pulse signal in which a level of reference potential of the on-pulse signal is shifted from primary side reference potential to secondary side reference potential;
• an off-side level shift circuit outputting a level shift off-pulse signal in which a level of reference potential of the off-pulse signal is shifted from the primary side reference potential to the secondary side reference potential;
• an on-side pulse transmission circuit outputting an on-pulse transmission signal based on the level shift on-pulse signal;
• an off-side pulse transmission circuit outputting an off-pulse transmission signal based on the level shift off-pulse signal;
• a dV/dt detection circuit detecting a dV/dt period which is a variation period of the secondary side reference potential based on the level shift on-pulse signal and the level shift off-pulse signal;
• a logic filter circuit which is provided in a latter stage of the on-side pulse transmission circuit and the off-side pulse transmission circuit and does not change an output when both the on-pulse transmission signal and the off-pulse transmission signal are input;
• and
• a latch circuit outputting a signal synchronized with an output of the logic filter circuit, wherein
• the on-side pulse transmission circuit includes an on-side impedance adjusting part reducing a signal level of the on-pulse transmission signal during the dV/dt period, and
• the off-side pulse transmission circuit includes an off-side impedance adjusting part reducing a signal level of the off-pulse transmission signal during the dV/dt period.