Mitigation of transient effects for wide load ranges

A method of improving transient response in a voltage regulator comprising:

• providing a regulated voltage at an output voltage terminal under a no-load condition;
• connecting a load to the output voltage terminal;
• converting a decrease in voltage at the output voltage terminal to a current signal;
• converting the current signal to a drive voltage with a dynamic impedance network having a dynamic impedance that is controlled by a bias current provided to the dynamic impedance network;
• increasing a drive current sourced to the output voltage terminal by providing the drive voltage to a drive transistor;
• adaptively reducing the dynamic impedance as the voltage at the output voltage terminal increases;
• and
• boosting the dynamic impedance after the voltage at the output voltage terminal reaches a nominal value by providing an offset current to the dynamic impedance network to reduce the bias current.

A system comprising:

• an electrical load that draws a load current;
• an output voltage terminal coupled to the electrical load;
• a first amplifier having first and second amplifier inputs, a bias terminal and a first amplifier output, the first amplifier input is coupled to a voltage reference, and the second amplifier input is coupled to the output voltage terminal;
• a second amplifier having a third amplifier input and a second amplifier output, the third amplifier input coupled to the first amplifier output;
• a first transistor having first and second transistor current terminals and a first control terminal, the first transistor current terminal is coupled to a supply voltage terminal, and the first control terminal is coupled to the second amplifier output;
• a second transistor having third and fourth transistor current terminals and a second control terminal, the third transistor current terminal coupled to the supply voltage terminal, the second control terminal is coupled to the first control terminal, and the fourth transistor current terminal is coupled to the output voltage terminal;
• a third transistor having fifth and sixth transistor current terminals and a third control terminal, the fifth transistor current terminal and the third control terminal are coupled to the second transistor current terminal, and the sixth current terminal is coupled to a ground terminal;
• a fourth transistor having seventh and eighth transistor current terminals and a fourth control terminal, the fourth control terminal is coupled to the third control terminal, and the eighth transistor current terminal is coupled to the ground terminal;
• a fifth transistor having ninth and tenth transistor current terminals and a fifth control terminal, the ninth current terminal coupled to the bias terminal of the first amplifier, the fifth control terminal is coupled to the third control terminal, and the tenth transistor current terminal is coupled to the ground terminal;
• a dynamic R-C network coupled between the third amplifier input and the seventh transistor current terminal, wherein the dynamic R-C network includes capacitors and MOS-based resistors;
• a third amplifier having a fourth amplifier input and a third amplifier output, the fourth amplifier input coupled to the output voltage terminal;
• and
• a capacitor coupled between the output voltage terminal and the fourth amplifier input.