US 2022/0102263 A1 · SEMICONDUCTOR PACKAGE HAVING A CHIP CARRIER WITH A PAD OFFSET FEATURE

Abstract

A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

Claims20

Dependent claims

A semiconductor package, comprising:

a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body;
and
a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential,
wherein the first pad is spaced inward from an edge of the semiconductor die by a first distance,
wherein the semiconductor die has an edge termination region between the edge and the first pad,
wherein the first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

3 more elements

A method of producing a semiconductor package, the method comprising:

providing a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body;
and
attaching a first pad of a semiconductor die to the first contact structure of the carrier, the first pad being at source or emitter potential,
wherein the first pad is spaced inward from an edge of the semiconductor die by a first distance,
wherein the semiconductor die has an edge termination region between the edge and the first pad,
wherein the first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/459,296Filed 27 Aug 2021

Priority

28 Sep 2020

Published

31 Mar 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10W 70/658
Shapes or dispositions of interconnections: for devices provided for in groups H10D8/00 - H10D48/00
H10W 90/401
Package configurations: characterised by multiple insulating or insulated package substrates, interposers or RDLs
H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10W 40/255
Characterised by their materials: having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates

Semiconductor package having a chip carrier with a pad offset feature

Life of this patent

Semiconductor package having a chip carrier with a pad offset feature

Life of this patent

Abstract

Claims20