Semiconductor packaging structure

A semiconductor packaging structure, comprising:

• a substrate which has an effective region and a dummy region surrounding said effective region;
• a wiring layer which is disposed on said effective region and said dummy region of said substrate, and which is formed with a predetermined pattern to expose a portion of said dummy region, said predetermined pattern including a plurality of protrusions that extend toward each other and that are spaced apart from each other to define at least one cavity;
• a mask layer which covers said wiring layer opposite to said substrate, and which is formed with at least one through hole to communicate in space with said cavity, said through hole having a size that is smaller than a size of said cavity, said through hole and said cavity cooperating to form an accommodating space;
• and
• a sealing layer which covers said mask layer and which includes an engaging element filling said accommodating space and adhering to said substrate.