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US 2022/0093504 A1Published application
Folded cell layout for 6t sram cell
AssigneeAdvanced Micro Devices, Inc.
InventorsRichard T. Schultz, John J. Wuu
Life of this patent
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Abstract
A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.
Claims20
A memory cell layout, comprising:
- a poly layer including an n-channel and a p-channel;
- a first metal layer, the first metal layer including:
- a first pair of bitlines spanning a width of a memory cell;
- and
- a first wordline, wherein the first wordline includes contacts at both ends of the first wordline;
- a second metal layer, the second metal layer including:
- a second wordline positioned on a side of the memory cell, wherein the second wordline spans a height of the memory cell, and wherein the second wordline connects to the first wordline;
- and
- a third metal layer including a second pair of bitlines spanning the width of the memory cell.
6 more elements
A system, comprising:
- at least one memory cell, the at least one memory cell including:
- a poly layer including an n-channel and a p-channel;
- a first metal layer, the first metal layer including:
- a first pair of bitlines spanning a width of a memory cell;
- and
- a first wordline, wherein the first wordline includes contacts at both ends of the first wordline;
- a second metal layer, the second metal layer including:
- a second wordline positioned on a side of the memory cell, wherein the second wordline spans a height of the memory cell, and wherein the second wordline connects to the first wordline;
- and
- a third metal layer including a second pair of bitlines spanning the width of the memory cell;
- and
- control logic coupled to the at least one memory cell.
9 more elements
A memory cell, comprising:
- a poly layer including an n-channel and a p-channel;
- a first metal layer, the first metal layer including:
- a first pair of bitlines spanning a width of a memory cell;
- and
- a first wordline, wherein the first wordline includes contacts at both ends of the first wordline;
- a second metal layer, the second metal layer including:
- a second wordline positioned on a side of the memory cell, wherein the second wordline spans a height of the memory cell, and wherein the second wordline connects to the first wordline;
- and
- a third metal layer including a second pair of bitlines spanning the width of the memory cell.
6 more elements
Dependencies are inferred from the claim text.