Memory module with reduced ecc overhead and memory system

A memory module comprising:

• a first data chip, a second data chip, a third data chip, a fourth data chip, a fifth data chip, a sixth data chip, a seventh data chip, an eighth data chip, a ninth data chip, a tenth data chip, an eleventh data chip, a twelfth data chip, a thirteenth data chip, a fourteenth data chip, a fifteenth data chip and a sixteenth data chip (inclusively, first to sixteenth data chips), each respectively configured to store data;
• a plurality of error correction code (ECC) chips configured to store ECC associated with the data;
• a registered clock driver (RCD) configured to control the plurality of ECC chips and the first to sixteenth data chips;
• and
• a plurality of input/output (I/O) pins mapped to the plurality of ECC chips and the first to sixteenth data chips,
• wherein first to eighth data chips among the first to sixteenth data chips are assigned to a first sub-channel, and ninth to sixteenth data chips among the first to sixteenth data chips are assigned to a second sub-channel, and
• the first to sixteenth data chips share the plurality of ECC chips.

A memory system, comprising:

• a memory module and a memory controller that controls operation of the memory module,
• wherein the memory module includes:
• data chips configured to store data and including a first set of data chips, a second set of data chips, wherein the first set of data chips is assigned to a first sub-channel that generates a first code word, the second set of data chips is assigned to a second sub-channel that generates a second code word, and the first code word and the second code fill a single cache line
• an error correction code (ECC) chip configured to store ECC associated with the data;
• and
• the memory controller is configured, upon detection of a hard-fail data chip among the data chips, to perform a chip-kill operation that copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding input/output (I/O) pins among a plurality of I/O pins, and defines new mapping between the ECC chip and the corresponding I/O pins.