US 2022/0093189 A1Published application

Semiconductor integrated circuit

AssigneeSocionext Inc.

InventorsMasanori Okinoi, Sachio Ogawa, Ryo Azumai, Kiichi Hamasaki

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Abstract

A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.

Claims16

Dependent claims

A semiconductor integrated circuit, comprising:

an output buffer configured to output a memory control signal, which is to be supplied to a memory device, to an external terminal coupled to the memory device;
a power supply control circuit configured to control a supply of a power supply voltage from a power supply line to the output buffer, based on a power control signal;
a pull-up control circuit configured to control a pull-up of the external terminal, based on a pull-up control signal;
and
a control signal generating circuit configured to
generate, during an output period in which the memory control signal is output to the external terminal, the power control signal which controls the power supply control circuit to supply the power supply voltage to the output buffer, and the pull-up control signal which controls the pull-up control circuit to stop the pull-up of the external terminal, and
generate, during an idle period in which the memory control signal is not output to the external terminal, the power control signal which controls the power supply control circuit to stop the supply of the power supply voltage to the output buffer, and the pull-up control signal which controls the pull-up control circuit to perform the pull-up of the external terminal.

4 more elements

A semiconductor integrated circuit comprising:

an output buffer configured to output a memory control signal, which is to be supplied to a memory device, to an external terminal coupled to the memory device, the output buffer including a p-channel MOS transistor;
a power supply control circuit including a power switch, coupled between a power supply line which supplies a power supply voltage, and a source of the p-channel MOS transistor of the output buffer, and configured to turn on or off based on a power control signal;
a pull-up control circuit including a pull-up switch, coupled between the power supply line and the external terminal, and configured to turn on or off based on a pull-up control signal, the pull-up switch functioning as a resistive element in an on state thereof;
and
a control signal generating circuit configured to generate the power control signal and the pull-up control signal during an output period in which the memory control signal is output to the external terminal, and an idle period in which the memory control signal is not output to the external terminal, based on a timing signal generated in correspondence with the output period.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/457,291Filed 2 Dec 2021
Priority: 12 Jun 2019
Published: 24 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 16/32
Auxiliary circuits, e.g. for writing into memory: timing circuits
G06F 12/00
Accessing, addressing or allocating within memory systems or architectures
G11C 5/148
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: details…
G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…

Family

Application17/457,291Continuation
US 11,798,635 B2Related patent
US 2022/0093189 A1This patent

From the US filing history. Foreign family members aren’t listed.

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