Pseudo-triple-port sram datapaths

A memory, comprising:

• a first bit line for a first column;
• a second bit line for the first column;
• the first column including a plurality of first bitcells, each first bitcell having a first read port coupled to the first bit line, a second read port coupled to the second bit line, and a write port coupled to the first bit line and to the second bit line;
• a first transmission gate having an output connected to the first bit line and an input for receiving a write data bit;
• and
• a second transmission gate having an output connected to the second bit line and an input for receiving a complement of the write data bit.

A method for a memory, comprising:

• in a read cycle responsive to a beginning of a cycle memory clock signal, performing a first single-ended read through a first bit line to a first bitcell in a column to charge the first bit line to a power supply voltage;
• while performing the first single-ended read, performing a second single-ended read through a second bit line to a second bitcell in the column to discharge the second bit line;
• and
• in a write cycle following the read cycle, writing to the first bitcell through the first bit line and through the second bit line, wherein the first bit line remains charged to the power supply voltage from an end of the read cycle to an end of the write cycle and the second bit line remains discharged from the end of the read cycle to the end of the write cycle.