Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device

A memory controller configured to control a multi-rank memory device, the multi-rank memory device including at least two memory ranks and each memory rank including a plurality of memory devices, the memory controller comprising:

• a clock signal line coupled to the multi-rank memory device and shared by the memory ranks;
• and
• a command/address (CA) signal line coupled to the multi-rank memory device and shared by the memory ranks,
• wherein the memory controller is configured to:
• transmit a first on-die termination (ODT) state information of the clock signal line and a second ODT state information of the CA signal line to the multi-rank memory device;
• and
• program the first and second ODT state information in first and second mode registers of each of the memory devices,
• wherein the first ODT state information has a first logic value when the clock signal line is terminated in at least one memory rank and has a second logic value when the clock signal line is unterminated in all of the memory ranks, and the second ODT state information has the first logic value when the CA signal line is terminated in at least one memory rank and has a second logic value when the CA signal line is unterminated in all of the memory ranks,
• wherein each memory device selects a first reference voltage for determining a logic level of the clock signal received through the clock signal line in response to the first ODT state information stored in the first mode register and selects a second reference voltage for determining a logic level of a CA signal received through the CA signal line in response to the second ODT state information stored in the second mode register, and
• wherein the first reference voltage is different from the second reference voltage when the first ODT state information and the second ODT state information have logic values different from each other.