Detection of data corruption in memory address decode circuitry
AssigneeIntel Corporation
InventorsSreenivas MANDAVA, Jing LING
Life of this patent
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Abstract
A memory controller including memory address decode circuitry that detects silent data errors that occur in the memory address decode circuitry during runtime is provided. The memory address decode circuitry includes address decode circuitry to covert a received physical address to a memory address, reverse address decode circuitry to convert the memory address to a second physical address and address compare circuitry to compare the received physical address and the second physical address to detect a silent error.
Claims20
A memory controller comprising:
- memory address decode circuitry, the memory address decode circuitry including:
- address decode circuitry to convert a received physical address to a memory address;
- reverse address decode circuitry to receive the memory address from the address decode circuitry and to convert the memory address to a second physical address;
- and
- address compare circuitry to compare the received physical address and the second physical address, the received physical address to be forwarded to a scheduler in the memory controller for use by a memory if the received physical address and the second physical address match.
A method performed by a memory controller comprising:
- converting, in address decode circuitry, a received physical address to a memory address;
- converting, in reverse address decode circuitry, the memory address to a second physical address;
- comparing, in address compare circuitry, the received physical address and the second physical address;
- and
- forwarding the received physical address to a scheduler in the memory controller for use by a memory if the received physical address and the second physical address match.
A system comprising:
- a processor, and
- a memory controller communicatively coupled to the processor, the memory controller comprising:
- memory address decode circuitry, the memory address decode circuitry including:
- address decode circuitry to convert a received physical address to a memory address;
- reverse address decode circuitry to receive the memory address from the address decode circuitry and to convert the memory address to a second physical address;
- and
- address compare circuitry to compare the received physical address and the second physical address, the received physical address to be forwarded to a scheduler in the memory controller for use by a memory if the received physical address and the second physical address match.
Dependencies are inferred from the claim text.