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US 2022/0069821 A1Published application
Pseudo-complementary logic network
AssigneePostech Research and Business Development Foundation
InventorsEun Hwan KIM, Jae-Joon KIM
Life of this patent
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Abstract
A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.
Claims16
A pseudo-complementary logic network comprising:
- a first logic stage comprising a first pull-up circuit of an N-type transistor and a first pull-down circuit;
- and
- a second logic stage comprising a second pull-up circuit and a second pull-down circuit of an N-type transistor,
- wherein
- an output signal of the second logic stage is provided as an input of the first pull-down circuit, and
- the first pull-up circuit comprises the second pull-down circuit.
3 more elements
A pseudo-complementary logic network comprising:
- a first logic stage comprising a first pull-down circuit of a P-type transistor and a first pull-up circuit;
- and
- a second logic stage comprising a second pull-down circuit and a second pull-up circuit of a P-type transistor,
- wherein
- an output signal of the second logic stage is provided as an input of the first pull-up circuit, and
- the first pull-down circuit comprises the second pull-up circuit.
3 more elements
Dependencies are inferred from the claim text.