US 2022/0068963 A1 · SEMICONDUCTOR MEMORY DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.

Claims25

Dependent claims

A semiconductor memory device comprising:

a bit line overlapping with a peripheral circuit layer;
interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line;
vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns;
a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels;
a source channel in contact with the connection pattern, the source channel extending in the first direction;
and
a source select line surrounding the source channel.

4 more elements

A semiconductor memory device comprising:

a word line including a first region, a second region, and a third region between the first region and the second region;
a first vertical channel penetrating the first region of the word line, the first vertical channel extending in a first direction;
a first connection pattern overlapping with the first region of the word line to be spaced apart from the word line in the first direction, the first connection pattern being in contact with a sidewall of the first vertical channel;
a first source channel in contact with the first connection pattern, the first source channel extending in the first direction;
and
a first source select line overlapping with the first region of the word line to be spaced apart from the first connection pattern in the first direction, the first source select line surrounding the first source channel.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and a manufacturing method of the semiconductor memory device

Life of this patent

Semiconductor memory device and a manufacturing method of the semiconductor memory device

Life of this patent

Abstract

Claims25