Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells

A method used in forming a memory array comprising strings of memory cells, comprising:

• forming a conductor tier comprising conductor material on a substrate;
• forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers;
• the lower portion comprising:
• a lowest of the second tiers directly above the conductor material, the lowest second tiers being sacrificial and comprising solid carbon and nitrogen-containing material;
• a lowest of the first tiers directly above the lowest second tier, the lowest first tier comprising sacrificial material that is of different composition from that of the lowest second tier;
• a next-lowest of the second tiers directly above the lowest first tier, the next-lowest second tier comprising the solid carbon and nitrogen-containing material;
• and
• a conducting-material tier comprising conducting material directly above the next-lowest second tier;
• forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion, and forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion;
• forming horizontally-elongated trenches into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the sacrificial material in the lowest first tier;
• isotropically etching the sacrificial material from the lowest first tier through the trenches;
• removing the lowest second tier and the next-lowest second tier after the isotropically etching;
• and
• after removing the lowest second tier and the next-lowest second tier, forming conductive material in the lowest first tier directly against a bottom of the conducting material of the conducting-material tier and directly against a top of the conductor material of the conductor tier to directly electrically couple together the channel material of the individual channel-material strings with the conductor material of the conductor tier and the conducting material of the conducting-material tier.

Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:

• laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the conductive tiers individually comprising a horizontally-elongated conductive line;
• and
• a second vertical stack aside the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising alternating first insulating tiers and second insulating tiers, the lower portion comprising:
• a lowest insulator tier directly above conductor material of a conductor tier, the lowest insulator tier comprising solid carbon and nitrogen-containing material;
• and
• an immediately-adjacent tier directly above the solid carbon and nitrogen-containing material of the lowest insulator tier, the immediately-adjacent tier comprising material that is of different composition from that of the lowest insulator tier.

Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:

• laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the conductive tiers individually comprising a horizontally-elongated conductive line;
• and
• a second vertical stack aside the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising alternating first insulating tiers and second insulating tiers, the lower portion comprising:
• a lowest insulator tier directly above conductor material of a conductor tier, the lowest insulator tier comprising solid carbon and nitrogen-containing material;
• an immediately-adjacent tier directly above the solid carbon and nitrogen-containing material of the lowest insulator tier, the immediately-adjacent tier comprising material that is of different composition from that of the lowest insulator tier;
• a next-lowest insulator tier directly above the immediately-adjacent tier, the next-lowest insulator tier comprising the solid carbon and nitrogen-containing material;
• and
• a conducting-material tier comprising conducting material directly above the immediately-adjacent tier.