US 2022/0068956 A1 · MEMORY DEVICE INCLUDING MULTIPLE DECKS OF MEMORY CELLS AND PILLARS EXTENDING THROUGH THE DECKS

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

Claims37

Dependent claims

An apparatus comprising:

a first deck located over a substrate, the first deck including first memory cells and first control gates associated with the first memory cells;
a second deck located over the first deck, the second deck including second memory cells and second control gates associated with the second memory cells;
pillars extending through the first control gates and the second control gates;
first conductive paths coupled to the first control gates, the first conductive paths including first conductive pads located on a first level of the apparatus over the substrate, each of the first conductive pads having a length in a direction perpendicular to a direction from the first deck to the second deck;
and
second conductive paths coupled to the second control gates, the second conductive paths including second conductive pads located on a second level of the apparatus over the first level, each of the second conductive pads having a length in the direction perpendicular to the direction from the first deck to the second deck.

3 more elements

An apparatus comprising:

first memory cells and first control gates associated with the first memory cells, the first control gates located on different levels of the apparatus;
second memory cells and second control gates associated with the second memory cells, the second memory cells and the second control gates located on different levels of the apparatus over the first memory cells and the first control gates;
third memory cells and third control gates associated with the third memory cells, the third memory cells and the third control gates located on different levels of the apparatus over the second memory cells and the second control gates;
pillars extending through the first control gates, the second control gates, and the third control gates;
first conductive paths including first conductive rails coupled to the first control gates, and first additional conductive rails coupled to the first conductive rails, the first conductive rails having different lengths in a first direction, the first additional conductive rails having different lengths in a second direction perpendicular to the first direction;
second conductive paths including second conductive rails coupled to the second control gates, and second additional conductive rails coupled to the second conductive rails, the second conductive rails and the second additional conductive rails located over the first conductive rails and the first additional conductive rails, the second conductive rails having different lengths in the first direction, the second additional conductive rails having different lengths in the second direction;
and
third conductive paths including third conductive rails coupled to the third control gates, and third additional conductive rails coupled to the third conductive rails, the third conductive rails and the third additional conductive rails located over the second conductive rails and the second additional conductive rails, the third conductive rails having different lengths in the first direction, the third additional conductive rails having different lengths in the second direction.

5 more elements

An apparatus comprising:

a dielectric structure including a length in a first direction, a first side and a second side opposite from the first side in a second direction perpendicular to the first direction;
a first additional dielectric structure located on the first side of the dielectric structure, the additional dielectric structure having a first wall;
a second additional dielectric structure located on the second side of the dielectric structure, the second additional dielectric structure having a second wall, wherein an angle between the first wall and the second wall is greater than zero and less than 180 degrees;
a first memory cell block located on the first side of the dielectric structure at a distance in the first direction from the first additional dielectric structure, the first memory cell block including first memory cells and first control gates located on different levels of the apparatus;
a second memory cell block located on the second side of the dielectric structure at a distance in the first direction from the second additional dielectric structure, the second memory cell block including second memory cells and second control gates located on different levels of the apparatus;
first conductive paths including first conductive rails coupled to the first control gates, the first conductive rails having lengths in the first direction;
and
second conductive paths including second conductive rails coupled to the second control gates, the second conductive rails having lengths in the first direction.

5 more elements

A method comprising:

forming first dielectric materials at first locations and second dielectric materials at second locations and interleaved with the first dielectric materials over a substrate, the first dielectric materials formed to include first portions and first additional portions perpendicular to the first portions;
forming third dielectric materials at third locations and fourth dielectric materials at fourth locations and interleaved with the third dielectric materials, the third and fourth dielectric materials formed over the first and second dielectric materials, the third dielectric materials formed to include third portions and third additional portions perpendicular to the third portions;
forming pillars through part of the first portions of the first dielectric materials, part of the second dielectric materials, part of the third portions of the third dielectric materials, and part of the fourth dielectric materials;
forming first memory cells at respective first portions along the lengths of the pillars, and second memory cells at respective second portions along the lengths of the pillars;
removing the first portions and first additional portions of the first dielectric materials at the first locations to form voids at the first locations;
removing the third portions and third additional portions of the third dielectric materials at the third locations to form voids at the third locations;
forming a fourth material in the voids at the first locations and the voids at the third locations, wherein:
a first portion of the fourth material at a first portion of the first locations forms first control gates associated with the first memory cells;
a second portion of the fourth material at a second portion of the first locations forms first conductive paths coupled to the first control gates;
a third portion of the fourth material at a first portion of the third locations forms second control gates associated with the second memory cells;
and
a fourth portion of the fourth material at a second portion of the third locations forms second conductive paths coupled to the second control gates.

9 more elements

A method comprising:

forming a first dielectric structure including walls extending outwardly from a substrate, the walls of the first dielectric structure having a zigzag pattern;
forming first dielectric materials and second dielectric materials interleaved with the first dielectric materials over the first dielectric structure, such that a first portion of the first and second dielectric materials is parallel to the substrate and a second portion the first and second dielectric materials is perpendicular to the first portion of the first and second dielectric materials and conformal to the walls of first dielectric structure;
removing part of the second portion of the first and second dielectric materials over the first dielectric structure to expose a remaining part of the second portion of the first dielectric materials;
forming first pad structures, such that each of the first pad structure contacts a respective portion of the first dielectric materials in the remaining part of the second portion of the first the dielectric materials;
forming an additional dielectric material over the first pad structures and over the first portion of the first and second dielectric materials;
forming a second dielectric structure over the additional dielectric material, the second dielectric structure including portions having walls extending outwardly from the substrate, the walls of the second dielectric structure having a zigzag pattern;
forming third dielectric materials and fourth dielectric materials interleaved with the third dielectric materials over the additional dielectric material, such that a first portion of the third and fourth dielectric materials is parallel to the substrate and a second portion of the third and fourth dielectric materials is perpendicular to the first portion of the third and fourth dielectric materials and conformal to the walls of second dielectric structure;
removing part of the second portion of the third and fourth dielectric materials over the second dielectric structure to expose a remaining part of the second portion of the third dielectric materials;
forming second pad structures, such that each of the second pad structures contacts a respective portion of the third dielectric materials in the remaining part of the second portion of the third dielectric materials;
forming pillars through the first portion of the first and second dielectric materials and the first portion of the third and fourth dielectric materials;
forming first memory cells along respective first portions of the pillars and second memory cells along respective second portions of the pillars;
replacing the first portion of the first dielectric materials at first locations and the remaining part of the of the second portion the first dielectric materials at second locations with a first portion of a conductive material to form first control gates at the first locations and first conductive paths at the second locations, wherein the first conductive paths are coupled to the first control gates, and the first control gates are adjacent respective memory cells of the second memory cells;
and
replacing the first portion of the third dielectric materials at third locations and the remaining part of the second portion of the third dielectric materials at fourth locations with a second portion of the conductive material to form second control gates at the third locations and second conductive paths at the fourth locations, wherein the second conductive paths are coupled to the second control gates, and the second control gates are adjacent respective memory cells of the second memory cells.

11 more elements

Dependencies are inferred from the claim text.

Memory device including multiple decks of memory cells and pillars extending through the decks

Life of this patent

Memory device including multiple decks of memory cells and pillars extending through the decks

Life of this patent

Abstract

Claims37