Memory and its manufacturing method
AssigneeChangxin Memory Technologies, Inc.
InventorJingwen LU
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure provide a memory and its manufacturing method. The memory includes: a substrate with a plurality of mutually discrete bitlines, the bitline including a bitline conductive layer and a bitline insulating layer which are stacked in sequence; and an insulating layer and capacitor contact holes, the insulating layer being located on sidewalls of the bitline conductive layers and sidewalls of the bitline insulating layers, the capacitor contact holes being located between adjacent ones of the bitline conductive layers, sidewalls of the capacitor contact holes exposing the insulating layer, an opening size of the capacitor contact hole gradually increasing in a direction along the substrate and towards the insulating layer.
Claims20
A manufacturing method of a memory, comprising:
- providing a substrate with a plurality of mutually discrete bitline conductive layers;
- forming an insulating layer, the insulating layer covering the bitline conductive layers and filling a region between adjacent ones of the bitline conductive layers, a top surface of the insulating layer being higher than the bitline conductive layer, and an etching rate of a subsequent second etching process for the insulating layer gradually increasing in a direction along the substrate and towards the insulating layer;
- carrying out a first etching process to etch the insulating layer located between the adjacent bitline conductive layers to form initial capacitor contact holes exposing the substrate;
- and
- carrying out the second etching process to etch the insulating layer on sidewalls of the initial capacitor contact holes to form capacitor contact holes, an opening size of the capacitor contact hole gradually increasing in the direction along the substrate and towards the insulating layer, the remaining insulating layer right above the bitline conductive layer serving as a bitline insulating layer.
A memory, comprising:
- a substrate with a plurality of mutually discrete bitlines, the bitline comprising a bitline conductive layer and a bitline insulating layer which are stacked in sequence;
- and
- an insulating layer and capacitor contact holes, the insulating layer being located on sidewalls of the bitline conductive layers and sidewalls of the bitline insulating layers, the capacitor contact holes being located between adjacent ones of the bitline conductive layers, sidewalls of the capacitor contact holes exposing the insulating layer, an opening size of the capacitor contact hole gradually increasing in a direction along the substrate and towards the insulating layer.
Dependencies are inferred from the claim text.