Integrated circuit devices and methods of manufacturing the same

A method of manufacturing an integrated circuit device, the method comprising:

• forming a semiconductor structure on a substrate;
• forming a mask pattern on the semiconductor structure;
• forming a fin-type active area comprising a portion of the substrate and a portion of the semiconductor structure, using the mask pattern as an etching mask, by etching the semiconductor structure and the substrate;
• forming a crystalline semiconductor layer extending on a surface of the fin-type active area with a first thickness and an amorphous semiconductor layer extending on a surface of the mask pattern with a second thickness that is greater than the first thickness;
• forming an isolation layer on the crystalline semiconductor layer and the amorphous semiconductor layer;
• forming an extended crystalline semiconductor layer on a side wall of the mask pattern by crystalizing a first portion of the amorphous semiconductor layer adjacent to an interface between the crystalline semiconductor layer and the amorphous semiconductor layer;
• removing a second portion of the amorphous semiconductor layer remaining on the extended crystalline semiconductor layer;
• removing the mask pattern;
• performing a recess process for removing a portion of the isolation layer such that a portion of the fin-type active area comprising the semiconductor structure protrudes upwardly beyond the isolation layer;
• and
• forming a semiconductor liner comprising a protrusion portion that protrudes outward and is adjacent to an edge of an upper surface of the fin-type active area by modifying the extended crystalline semiconductor layer and the crystalline semiconductor layer while performing the recess process.

A method of manufacturing an integrated circuit device, the method comprising:

• forming a stacked structure on a substrate, the stacked structure comprising a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers that are stacked alternately with the plurality of sacrificial semiconductor layers;
• forming a mask pattern on the stacked structure;
• forming a fin-type active area comprising a first portion of the substrate, using the mask pattern as an etching mask, by etching a first portion of the stacked structure and a second portion of the substrate;
• forming a crystalline semiconductor layer extending on, with a first thickness, the fin-type active area and the stacked structure remaining on the fin-type active area and an amorphous semiconductor layer extending on the mask pattern with a second thickness that is greater than the first thickness;
• forming an isolation layer on the crystalline semiconductor layer and the amorphous semiconductor layer;
• forming an extended crystalline semiconductor layer on a side wall of the mask pattern by crystalizing a first portion of the amorphous semiconductor layer adjacent to an interface between the crystalline semiconductor layer and the amorphous semiconductor layer;
• removing a second portion of the amorphous semiconductor layer remaining on the extended crystalline semiconductor layer;
• removing the mask pattern;
• performing a recess process for removing a portion of the isolation layer such that a second portion of the stacked structure protrudes upwardly beyond the isolation layer;
• and
• forming a semiconductor liner comprising a protrusion portion that protrudes outward and is adjacent to an edge of an upper surface of an uppermost one of the plurality of nanosheet semiconductor layers by modifying the extended crystalline semiconductor layer and the crystalline semiconductor layer while performing the recess process.