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US 2022/0068843 A1Published application
Substrate cores for warpage control
AssigneeIntel Corporation
InventorsSeok Ling LIM, Bok Eng CHEAH, Jackson Chung Peng KONG, Jenny Shio Yin ONG
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Abstract
According to the various aspects, a package substrate with a heterogeneous substrate core including a first core layer that is coextensive with the package substrate and extends through a first section and a second section of the substrate core, in which the first section is adjacent to and thicker than the second section. The first section having at least a second layer and/or a third layer to provide the difference in thickness with the second section.
Claims20
A package substrate comprising:
- a heterogeneous substrate core in the package substrate, the heterogeneous substrate core comprising:
- a first core layer comprising a top surface and a bottom surface, wherein the first core layer is coextensive with the package substrate;
- a first core section adjacent to a second core section, wherein the first core section is thicker than the second core section and wherein the first core layer extends through the first and second core sections of the heterogeneous substrate core;
- and
- at least one plated through hole via in the heterogeneous substrate core;
- and
- a plurality of level interconnects and micro-vias in the package substrate.
4 more elements
A computing device comprising:
- a printed circuit board;
- a semiconductor package on the printed circuit board, the semiconductor package comprising:
- a package substrate, the package substrate comprising:
- a heterogeneous substrate core in the package substrate, the heterogeneous substrate core comprising:
- a first core section adjacent to a second core section, wherein
- the first core section is thicker than the second core section;
- a first core layer comprising a top surface and a bottom surface in the heterogeneous substrate core, wherein the first core layer is coextensive with the substrate and extends through the first and second core sections of the heterogeneous substrate core;
- and
- a plurality of plated through hole vias in the heterogeneous substrate core;
- and
- a plurality of level interconnects and micro-vias formed in the package substrate;
- and
- a plurality of semiconductor devices coupled to the package substrate.
10 more elements
A method comprising:
- forming a heterogeneous substrate core for a package substrate, wherein the forming of the heterogeneous substrate core further comprises:
- providing a first core layer with a top surface and a bottom surface that is coextensive with the package substrate;
- and
- forming first and second core sections in the heterogeneous substrate core, wherein the first core section is adjacent to and thicker than the second core section and wherein the first core layer extends through the first and second core sections.
1 more element
Dependencies are inferred from the claim text.