Via for semiconductor device and method

An integrated circuit structure comprising:

• a first inter-metal dielectric layer (IMD) over a substrate;
• a metal line in the first IMD;
• a second IMD over the first IMD;
• and
• a via in the second IMD, wherein the via physically contacts the metal line, wherein the via comprises:
• a filling material comprising a first conductive material;
• a first adhesion layer extending between the filling material and the metal line, wherein the first adhesion layer comprises a second conductive material;
• and
• a diffusion barrier layer extending between the filling material and the second IMD, wherein the first adhesion layer and the metal line are free of the diffusion barrier layer, wherein the diffusion barrier layer overhangs the first adhesion layer, wherein the diffusion barrier layer comprises a third conductive material that is a different conductive material than the second conductive material.

A method of forming a semiconductor device, the method comprising:

• forming a conductive feature in a first dielectric layer;
• forming a second dielectric layer over the first dielectric layer;
• etching an opening through the second dielectric layer, the etching exposing a surface of the conductive feature;
• depositing a metal adhesion layer in the opening, wherein the metal adhesion layer covers the exposed surface of the conductive feature;
• depositing a sacrificial layer in the opening, wherein the sacrificial layer forms more selectively on the metal adhesion layer than on surfaces of the second dielectric layer;
• depositing a barrier layer in the opening, wherein the barrier layer forms more selectively on surfaces of the second dielectric layer than on the sacrificial layer;
• removing the sacrificial layer;
• and
• depositing a conductive material to fill the opening, wherein the conductive material covers the metal adhesion layer.