Different scaling ratio in feol / mol/ beol

An integrated chip, comprising:

• a first gate contact arranged over a substrate and having a first upper surface;
• a second gate contact arranged over the substrate and having a second upper surface;
• a first via arranged on the first upper surface, wherein the first upper surface extends to a first maximum distance past an outermost sidewall of the first via in a first direction;
• and
• a second via arranged on the second upper surface, wherein the second upper surface extends to a second maximum distance past an outermost sidewall of the second via in a second direction that is opposite the first direction.

A method for generating a scaled integrated chip design, comprising:

• forming an original integrated chip (IC) design comprising a graphical representation of a layout corresponding to an integrated chip to be formed on a semiconductor substrate, wherein the original IC design comprises a gate contact layer comprising a plurality of gate contacts and a first interconnect layer comprising a first plurality of interconnects;
• scaling the gate contact layer at a first scaling ratio;
• and
• scaling the first interconnect layer at a second scaling ratio that is different than the first scaling ratio.