Multi-chip package with extended frame
AssigneeIntel Corporation
InventorsBok Eng CHEAH, Seok Ling LIM, Jackson Chung Peng KONG, Jenny Shio Yin ONG, Kooi Chi OOI
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AssigneeIntel Corporation
InventorsBok Eng CHEAH, Seok Ling LIM, Jackson Chung Peng KONG, Jenny Shio Yin ONG, Kooi Chi OOI
Estimating the term…
According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.
A device comprising:
A computing device comprising:
A method comprising:
Dependencies are inferred from the claim text.