Bcd ic with gate etch and self-aligned implant integration

A method of fabricating an integrated circuit (IC), comprising:

• providing a substrate including a semiconductor surface having well diffusions for a plurality of devices, the plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices;
• depositing a polysilicon layer on a dielectric layer over the semiconductor surface;
• forming anti-reflective coating (ARC) layers on the polysilicon layer comprising forming a bottom ARC layer and then forming a top ARC layer on the bottom ARC layer that is a different material compared to the bottom ARC layer;
• forming a photoresist pattern on the top ARC layer;
• etching the ARC layers in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layers on the polysilicon layer;
• removing the photoresist pattern;
• etching the polysilicon layer in areas lacking the ARC layers to form polysilicon gates having a remaining ARC portion of the ARC layer thereon, wherein a thickness of the remaining ARC portion is at least 50% of a thickness of the ARC layers before the etching of the polysilicon layer, and wherein the remaining ARC portion is at a sidewall taper angle of at least 80 degrees relative to a top surface of the polysilicon gates;
• performing at least one self-aligned ion implantation using the remaining ARC portion as an additional implant blocking layer for the polysilicon gates,
• forming a spacer on sidewalls of the polysilicon gates and then performing an additional ion implant, and
• stripping the remaining ARC portion.