Circuit and method for process and temperature compensated read voltage for non-volatile memory

A method, comprising:

• driving a current through a replica bitline current path coupled to a replica memory cell;
• generating a read voltage with an operational amplifier coupled to a data storage node of the replica memory cell;
• and
• supplying the read voltage to a wordline of a memory array including a plurality of memory cells, the replica memory cell being a replica of the memory cells;
• receiving, at a first input terminal of the operational amplifier, a first voltage from an intermediate node of the replica bitline current path;
• and
• receiving at a second input terminal of the operational amplifier, a second voltage from a reference voltage regulator.

An integrated circuit, comprising:

• a non-volatile memory array including:
• a plurality of memory cells;
• a plurality of wordlines;
• and
• a plurality of bitlines;
• and
• a read voltage regulator configured to generate a read voltage and to apply the read voltage to the wordlines of the memory array during a read operation, the read voltage regulator including:
• a replica memory array having a replica memory cell;
• a replica bitline coupled to the replica memory array;
• a replica column decoder transistor in a current path of the replica bitline;
• a replica sense amplifier transistor in the current path of the replica bitline;
• and
• an operational amplifier coupled to a gate terminal of the replica memory cell a resistor and configured to supply the read voltage.