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US 2022/0068391 A1Published application
Programming techniques for polarity-based memory cells
AssigneeMicron Technology, Inc.
InventorsInnocenzo Tortorelli, Mattia Boniardi, Mattia Robustelli
Life of this patent
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Abstract
Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.
Claims25
A method, the method comprising:
- receiving, at a memory device, a command to write a first set of memory cells at the memory device to a first state and a second set of memory cells at the memory device to a second state;
- performing a first write operation on the first set of memory cells based at least in part on the command, wherein performing the first write operation comprises:
- applying a first pulse having a first polarity to the first set of memory cells;
- identifying, based at least in part on applying the first pulse and within the first set of memory cells, a subset of memory cells that are in the second state;
- and
- applying, based at least in part on the identifying, a second pulse having a second polarity to the subset of memory cells to write the subset of memory cells to the first state;
- performing, concurrent with the first write operation, a second write operation on the second set of memory cells based at least in part on the command, wherein performing the second write operation comprises:
- applying a third pulse having the second polarity to the second set of memory cells;
- and
- applying, after applying third pulse, a fourth pulse having the first polarity to the second set of memory cells to write the second set of memory cells to the second state.
7 more elements
A method, the method comprising:
- receiving, at a memory device, a write command to write a first set of memory cells at the memory device to a first state;
- applying, based at least in part on the command, a first pulse having a first polarity to the first set of memory cells;
- identifying, based at least in part on applying the first pulse and within the first set of memory cells, a first subset of memory cells that are in a second state;
- applying a second pulse having the first polarity to the first subset of memory cells based at least in part on identifying the first subset of memory cells;
- identifying, based at least in part on applying the second pulse and within the first subset of memory cells, a second subset of memory cells that remain in the second state;
- applying a third pulse having a second polarity to the second subset of memory cells based at least in part on identifying the second subset of memory cells;
- and
- applying, after applying the third pulse, a fourth pulse having the first polarity to the second subset of memory cells to write the second subset of memory cells to the first state.
5 more elements
An apparatus, comprising:
- a memory array;
- and
- a controller coupled with the memory array and configured to cause the apparatus to:
- receive a command to write a first set of memory cells within the memory array to a first state and a second set of memory cells within the memory array to a second state;
- perform a first write operation on the first set of memory cells based at least in part on the command, wherein, to perform the first write operation, the controller is configured to cause the apparatus to:
- apply a first pulse having a first polarity to the first set of memory cells;
- identify, based at least in part on applying the first pulse and within the first set of memory cells, a subset of memory cells that are in the second state;
- and
- apply, based at least in part on the identifying the subset of memory cells, a second pulse having a second polarity to the subset of memory cells to write the subset of memory cells to the first state;
- and
- perform, concurrent with the first write operation, a second write operation on the second set of memory cells based at least in part on the command, wherein, to perform the second write operation, the controller is configured to cause the apparatus to:
- apply a third pulse having the second polarity to the second set of memory cells;
- and
- apply, after applying third pulse, a fourth pulse having the first polarity to the second set of memory cells to write the second set of memory cells to the second state.
11 more elements
An apparatus, comprising:
- a memory array;
- and
- a controller coupled with the memory array and configured to cause the apparatus to:
- receive a command to write a first set of memory cells within the memory array to a first state and a second set of memory cells within the memory array to a second state;
- apply, based at least in part on the write command, a first pulse having a first polarity to the first set of memory cells and the second set of memory cells;
- apply a second pulse having the first polarity to a first subset of memory cells within the first set of memory cells, the first subset of memory cells identified as being in the second state based at least in part on the first pulse;
- apply a third pulse having a second polarity to a second subset of memory cells within the second set of memory cells, the second subset of memory cells identified as being in the first state based at least in part on the first pulse;
- apply a fourth pulse having the second polarity to a third subset of memory cells within the first set of memory cells, the third subset of memory cells identified as remaining in the second state based at least in part on the second pulse;
- apply a fifth pulse having the first polarity to a fourth subset of memory cells within the second set of memory cells, the fourth subset of memory cells identified as remaining in the first state based at least in part on the third pulse;
- apply, after the fourth pulse, a sixth pulse having the first polarity to the third subset of memory cells to write the third subset of memory cells to the first state;
- and
- apply, after the fifth pulse, a seventh pulse having the second polarity to the fourth subset of memory cells to write the fourth subset of memory cells to the second state.
9 more elements
Dependencies are inferred from the claim text.