Decoding for pseudo-triple-port sram

A method of word line decoding for a memory, comprising:

• in a first logic gate, processing a first pre-decoded first word line address and a first word line clock signal;
• asserting a first word line in a first word line pair for a first bitcell during a first word line assertion period in a cycle of a memory clock signal responsive to the processing of the first pre-decoded first word line address and the first word line clock signal;
• in the first logic gate, processing a second pre-decoded first word line address and the first word line clock signal;
• asserting the first word line in the first word pair during a second word line assertion period in the cycle of the memory clock signal responsive to the processing of the second pre-decoded first word line address and the first word line clock signal;
• in a second logic gate, processing a pre-decoded second word line address and a second word line clock signal;
• and
• asserting a second word line in the first word pair during the second word line assertion period in the cycle of the memory clock signal responsive to the processing of the pre-decoded second word line address and the second word line clock signal.

A memory, comprising:

• a column including a plurality of bitcells;
• a first bit line;
• a second bit line;
• a plurality of word line pairs corresponding to the plurality of bitcells, each bitcell having a first read port coupled to the first bit line through a first access transistor configured to be controlled by a first word line in the corresponding word line pair, each bitcell having a second read port coupled to the second bit line through a second access transistor configured to be controlled by a second word line in the corresponding word line pair;
• and
• a word line decoder including a plurality of logic gate pairs corresponding to the plurality of word line pairs, each logic gate pair comprising a first logic gate configured to assert the first word line in the corresponding word line pair and a second logic gate configured to assert the second word line in the corresponding word line pair, the word line decoder further including a plurality of third logic gates corresponding to the plurality of word line pairs, each third logic gate in the plurality of logic gates having an output node connected to a gate of the first access transistor in a respective bitcell from the plurality of bitcells.