Systems and methods for level down shifting drivers

A method for manufacturing a level down shifting driver circuit, comprising:

• manufacturing an input circuitry having at least one input port;
• manufacturing a cross junction circuitry electrically coupled to the input circuitry and configured to receive a first signal from the input circuitry to drive one or more devices included in the cross-junction circuitry, wherein the one or more devices are electrically coupled via a cross-junction;
• and
• manufacturing an output drive circuitry electrically coupled to the cross junction circuitry and configured to receive a second signal from the cross junction circuitry, wherein the output drive circuitry comprises an output line configured to deliver a first voltage output based on a first input voltage received by the input circuitry, and a second voltage output based on a second input voltage received by the input circuitry, wherein the first or the second voltage outputs are at a lower voltage than the first or the second input voltages, and wherein the output line does not include a feedback loop.

A level down shifting driver circuit, comprising:

• a first pull-up power supply;
• a second pull-up power supply lower than the first pull-up power supply;
• a first pull-down power supply;
• a second pull-down power supply lower than the first pull-down power supply;
• a cross-junction circuitry including:
• a first input node,
• a first output node,
• a first pull-up transistor coupled between the first pull-up power supply and the first output node, a gate of the first pull-up transistor being coupled to the first input node;
• and
• a first pull-down transistor coupled between the first pull-down power supply and the first output node, a gate of the first pull-down transistor being coupled to the first input node;
• a level shifting circuitry including:
• a second output node,
• a second pull-down transistor coupled between the second pull-down power supply and the second output node, a gate of the second pull-down transistor being coupled to the first input node;
• and
• an output device circuitry including:
• a third output node;
• a second pull-up transistor coupled between the second pull-up power supply and the third output node, a gate of the second pull-up transistor being coupled to the second output node;
• and
• a third pull-down transistor coupled between the second pull-down power supply and the third output node, a gate of the third pull-down transistor being coupled, at least in part, to the second output node.