Methods and Systems for Improving Read and Write of Memory Cells
AssigneeMicron Technology, Inc.
InventorsFerdinando Bedeschi, Riccardo Muzzetto, Umberto di Vincenzo
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Abstract
A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.
Claims28
A method for accessing an array of memory cells wherein a set of user data is stored in a plurality of memory cells of the memory array, comprising:
- latching a current row address of a selected plurality of memory access;
- comparing a last row address with the current row address;
- if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry;
- and
- if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.
A method for programming an array of memory cells wherein a codeword of user data is stored in the memory array, comprising:
- executing first a writing algorithm for “0” logic values of the codeword;
- executing a subsequent writing algorithm for “1” logic values of the codeword;
- and
- latching a last row access address.
A memory device comprising:
- an array of memory cells;
- at least a codeword in the memory array including a set of user data and additional data information;
- a memory controller configured to execute instructions for accessing the memory cells;
- and
- a circuit for accessing the memory cells, the circuit being operatively coupled with the array of memory cells and comprising at least:
- an access circuit configured to apply to the memory array a read voltage to activate at least said codeword of memory cells;
- and
- a sense circuit configured to support precharging and reading operations on said codeword;
- wherein, said sense circuit is structured with a leakage compensation circuit portion to avoid false reading of the cells of the codeword.
Dependencies are inferred from the claim text.