Display driver

A display driver, having first to kth output channels outputting first to kth pixel driving voltages respectively corresponding luminance levels of respective pixels indicated in a video signal, k being an integer of 2 or more, the display driver comprising:

• an output timing control part, generating first to kth output timing signals indicating output timings at the respective first to kth output channels;
• and
• an output part, respectively outputting the first to kth pixel driving voltages at the output timings indicated in the respective first to kth output timing signals,
• wherein the output timing control part comprises:
• a control signal generation part, receiving a designation of the output timing at each of the first to kth output channels and generating a first delay pulse signal at the output timing of the first output channel that is designated and generating a second delay pulse signal at the output timing of the kth output channel that is designated;
• a first delay generation part, receiving the first delay pulse signal, and generating first to kth first direction delay shift signals in which the first delay pulse signal is present after a delay increased by a unit delay time for each output channel from the first output channel to the kth output channel,
• a second delay generation part, receiving the second delay pulse signal, and generating first to kth second direction delay shift signals in which the second delay pulse signal is present after the delay increased by the unit delay time for each output channel from the kth output channel to the first output channel, and
• a delay selection part, for each of the first to kth output channels, selecting one signal whose timing at which the delay pulse signal is present is earlier from each of the first to kth first direction delay shift signals and each of the first to kth second direction delay shift signals that are signals corresponding to the same output channel, and outputting the selected signals for the respective first to kth output channels as the first to kth output timing signals.