US 2022/0067266 A1 · STANDARD CELLS AND VARIATIONS THEREOF WITHIN A STANDARD CELL LIBRARY

Abstract

Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Claims20

Dependent claims

A method for fabricating an electronic device onto a semiconductor substrate, the method comprising:

receiving, by a computer system, a standard cell library having a standard cell and a standard cell variation corresponding to the standard cell from a semiconductor foundry, the standard cell and the standard cell variation were developed to occupy different arrangements of a plurality of legal sites of the electronic architectural design;
developing, by the computer system, an electronic architectural design for the electronic device utilizing the standard cell library;
forming, by the computer system, one or more semiconductor devices of the electronic device within or onto the semiconductor substrate in accordance with the electronic architectural design;
forming, by the computer system, one or more local interconnections in accordance with the electronic architectural design for electrically connecting the one or more semiconductor devices;
and
forming, by the computer system, one or more global interconnections between the one or more local interconnections in accordance with the electronic architectural design to form the electronic device.

3 more elements

A system for fabricating an electronic device onto a semiconductor substrate, the system comprising:

a memory that stores an electronic architectural design for the electronic device that was developed utilizing a standard cell library having a standard cell and a standard cell variation that corresponds to the standard cell, the standard cell and the standard cell variation being developed to occupy different arrangements of a plurality of legal sites of the electronic architectural design;
and
a processor configured to execute one or more electronic design software applications, the one or more electronic design software applications, when executed by the processor, configuring the processor to:
form one or more semiconductor devices of the electronic device within or onto the semiconductor substrate in accordance with the electronic architectural design,
form one or more local interconnections in accordance with the electronic architectural design for electrically connecting the one or more semiconductor devices, and
form one or more global interconnections between the one or more local interconnections in accordance with the electronic architectural design to form the electronic device.

3 more elements

Dependencies are inferred from the claim text.

Standard cells and variations thereof within a standard cell library

Life of this patent

Standard cells and variations thereof within a standard cell library

Life of this patent

Abstract

Claims20