Variation-aware delay fault testing

A method comprising:

• identifying a shortlist of long paths from an input netlist, the shortlist of long paths comprising paths through each potential fault site having a nominal slack in an absence of process variations that is less than a threshold and being a real path testable by a test pattern;
• for each path of the shortlist of long paths, performing long path selection by:
• generating a specified number of random variation scenarios, wherein a random variation scenario (RVS) is an instance of the input netlist where values for a set of process parameters for each gate in the path are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter, wherein across different RVSs, the values for the set of process parameters are independently chosen for each gate in the path;
• calculating a total delay through the path for each RVS of the specified number of RVSs;
• and
• selecting a number of paths having highest total delays for each fault site under random variations of the RVSs, wherein the number of paths is at least two paths having the highest total delays;
• and
• generating delay test patterns for each of the selected paths for each fault site.

A system comprising:

• a processor;
• memory;
• a delay library stored on the memory, the delay library comprising mapping data structures, each mapping data structure indicating a nominal value and a distribution for each particular process parameter of a set of process parameters for each gate;
• and
• instructions for an electronic design automation tool stored on the memory that when executed by the processor, direct the processor to:
• perform long path selection by:
• generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for the set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate stored in the delay library, wherein across different RVSs, the values for the set of process parameters are independently chosen for each gate in a path;
• calculating a total delay through a path for each RVS;
• and
• selecting a number of paths having highest total delays for each fault site under random variations of the RVSs, wherein the number of paths is at least two paths having the highest total delays;
• and
• generate delay test patterns for each of the selected paths for each fault site.