US 2022/0067156 A1 · PROCESSOR THAT MITIGATES SIDE CHANNEL ATTACKS BY PREVENTING CACHE MEMORY STATE FROM BEING AFFECTED BY A MISSING LOAD OPERATION BY INHIBITING OR CANCELING A FILL REQUEST OF THE LOAD OPERATION IF AN OLDER LOAD GENERATES A NEED FOR AN ARCHITECTURAL EXCEPTION

Abstract

An out-of-order and speculative execution microprocessor that mitigates side channel attacks includes a cache memory and fill request generation logic that generates a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory. At least one execution pipeline receives first and second load operations, detects a condition in which the first load generates a need for an architectural exception, the second load misses in the cache memory, and the second load is newer in program order than the first load, and prevents state of the cache memory from being affected by the miss of the second load by inhibiting the fill request generation logic from generating a fill request for the second load or by canceling the fill request for the second load if the fill request generation logic has already generated the fill request for the second load.

Claims21

Dependent claims

A microprocessor that mitigates side channel attacks, comprising:

a cache memory;
fill request generation logic configured to generate a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory;
wherein the processor is configured to perform speculative execution of instructions;
wherein the processor is configured to execute instructions out of program order;
and
at least one execution pipeline configured to:
receive first and second load operations;
detect a condition in which the first load operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the first load operation;
and
prevent state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation.

7 more elements

A method for mitigating side channel attacks in a microprocessor having a cache memory, at least one execution pipeline, and fill request generation logic configured to generate a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory, comprising:

wherein the processor is configured to perform speculative execution of instructions;
wherein the processor is configured to execute instructions out of program order;
and
receiving, by the at least one execution pipeline, first and second load operations;
detecting, by the at least one execution pipeline, a condition in which the first load operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the first load operation;
and
preventing, by the at least one execution pipeline, state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation.

4 more elements

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor for mitigating side channel attacks, the microprocessor having a cache memory, at least one execution pipeline, and fill request generation logic configured to generate a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory, wherein the microprocessor is configured by the instructions to perform operations comprising:

wherein the processor is configured to perform speculative execution of instructions;
wherein the processor is configured to execute instructions out of program order;
and
receiving, by the at least one execution pipeline, first and second load operations;
detecting, by the at least one execution pipeline, a condition in which the first load operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the first load operation;
and
preventing, by the at least one execution pipeline, state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation.

4 more elements

Dependencies are inferred from the claim text.

Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception

Life of this patent

Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception

Life of this patent

Abstract

Claims21