Distributed multi-die protocol application interface

A method comprising:

• communicating data between an input/output (I/O) die and an integrated circuit die over a communication bus comprising a plurality of channels and a clock signal line, wherein:
• the I/O die comprises a first bus interface coupled to the communication bus, a second bus interface coupled to a memory, and an on-die interconnect coupling the first bus interface to the second bus interface;
• the integrated circuit die comprises a third bus interface, the third bus interface coupling the integrated circuit die to the first bus interface over the communication bus;
• and
• the plurality of channels of the communication bus comprise a first plurality of unidirectional channels from the first bus interface to the third bus interface and a second plurality of unidirectional channels from the third bus interface to the first bus interface;
• transmitting, from the first bus interface to the third bus interface using the communication bus, source synchronous data comprising a plurality of data signals;
• synchronizing, by the third bus interface, the plurality of data signals of the source synchronous data by latching the received source synchronous data using a clock signal transmitted from the first bus interface over the clock signal line;
• and
• separately setting a clock frequency associated with the second bus interface and a clock frequency associated with the on-die interconnect.

A system comprising:

• a memory device;
• a communication bus comprising a plurality of channels and a clock signal line;
• an input/output (IO) die comprising:
• a first bus interface coupled to the communication bus, wherein the first bus interface is configurable to transmit source synchronous data comprising a plurality of data signals over a first plurality of unidirectional channels of the plurality of channels;
• a second bus interface to couple the IO die to the memory device;
• and
• an on-die interconnect to couple the first bus interface to the second bus interface;
• and
• an integrated circuit die comprising a third bus interface to couple the integrated circuit die to the first bus interface over the communication bus and receive the plurality of data signals via the first plurality of unidirectional channels, wherein the third bus interface comprises circuitry to synchronize the plurality of data signals of the source synchronous data by latching the received source synchronous data using a clock signal transmitted from the first bus interface over the clock signal line;
• and
• wherein a clock frequency associated with the second bus interface and a clock frequency associated with the on-die interconnect are separately settable, and
• wherein in a first configuration, the clock frequency associated with the second bus interface is different from the clock frequency associated with the on-die interconnect, and in a second configuration, the clock frequency associated with the on-die interconnect and the clock frequency associated with the second bus interface are the same.