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US 2022/0066943 A1Published application
Banked memory architecture for multiple parallel datapath channels in an accelerator
AssigneeMicrosoft Technology Licensing, LLC
InventorsStephen Sangho YOUN, Steven Karl REINHARDT, Hui GENG
Life of this patent
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Abstract
The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.
Claims20
A banked memory structure for use with an accelerator, comprising:
- a plurality of local memory, wherein the plurality of local memory includes a memory decoder;
- a plurality of computation units;
- and
- a plurality of channels, wherein each channel of the plurality of channels is paired with a separate local memory of the plurality of local memory and one computation unit of the plurality of computation units, wherein
- the memory decoder receives data for the accelerator, wherein the data includes a plurality of vectors and each vector of the plurality of vectors is assigned by the memory decoder to one channel of the plurality of channels for processing by the computation unit associated with the channel.
2 more elements
A method performed by a memory decoder of an accelerator, comprising:
- receiving data for use with the accelerator;
- identifying a plurality of vectors for the data;
- identifying a plurality of local memory in the accelerator;
- for each vector of the plurality of vectors:
- selecting a separate local memory of the plurality of local memory for use with the vector;
- mapping an address of the separate local memory to the vector;
- and
- using the mapping to send the data for the vector to a data channel associated with the separate local memory.
5 more elements
A device, comprising:
- one or more processors;
- memory in electronic communication with the one or more processors;
- and
- instructions stored in the memory, the instructions being executable by the one or more processors to:
- receive data for use with an accelerator;
- identify a plurality of vectors for the data;
- identify a plurality of local memory in the accelerator;
- for each vector of the plurality of vectors:
- select a separate local memory of the plurality of local memory for use with the vector;
- map an address of the separate local memory to the vector;
- and
- use the mapping to send the data for the vector to a data channel associated with the separate local memory.
9 more elements
Dependencies are inferred from the claim text.