Multi-way cache memory access

Peripheral circuitry for providing access to a cache memory by a central processing unit (CPU), the peripheral circuitry comprising:

• one or more CPU busses by which to receive a CPU address corresponding to a request for retrieval of an instruction from the cache memory, the CPU address having a tag portion and an index portion;
• tag peripheral circuitry configured to:
• detect an active tag clock signal indicating a first part of a CPU clock cycle;
• retrieve, responsive to the detecting the active tag clock signal, M tags from the cache memory, each of the M tags identifying a corresponding one of M ways of the cache memory, where M is an integer greater than one;
• and
• compare the M tags to the tag portion of the CPU address to determine whether there is a matching tag of the M tags that corresponds to a matching way of the M ways;
• and
• instruction peripheral circuitry configured to:
• detect an active instruction clock signal indicating a second part of the CPU clock cycle;
• and
• perform, responsive to the detecting the active instruction clock signal, a read operation, based on the index portion of the CPU address, to retrieve the instruction from an instruction memory portion of the matching way of the cache memory.