Electronic device, system-on-chip, and operating method thereof

An operating method of an electronic device which includes a cache memory including a memory space configured to store a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data stored in the cache memory are modified, a memory device, and a memory controller between the cache memory and the memory device, the method comprising:

• setting, by the memory controller, a logic level of the data mask signal based on a logic level of each of the plurality of dirty bits;
• issuing, by the memory controller, a first mask write (MWR) command to the memory device through command/address (CA) lines connected thereto;
• and
• transmitting, by the memory controller, the plurality of sector data stored in the cache memory to the memory device through a plurality of data lines connected thereto, and a data mask signal to the memory device through a data mask line connected thereto.

A solid state drive (SSD) controller comprising:

• a cache memory including a memory storage configured to store a first cache set including first sector data and second sector data, and a first dirty bit and a second dirty bit which are associated with the first sector data and the second sector data, respectively;
• and
• a buffer memory interface circuit configured to flush, based on a logic level of each of the first and second dirty bits, the first and second sector data to an external memory device,
• wherein. wherein, when the first dirty bit indicates a dirty state and the second dirty bit indicates a clean state, the buffer memory interface circuit masks the first sector data to generate first masked sector data, outputs the first masked sector data to the external memory device through a plurality of data lines during a first time period, and outputs the second sector data to the external memory device through the plurality of data lines during a second time period.

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• an input/output circuit configured to receive a plurality of sector data through a plurality of data lines;
• and
• a control logic circuit configured to:
• receive a first mask write (MWR) command through command/address (CA) lines;
• receive a data mask signal through a data mask line;
• and
• selectively store the plurality of sector data in the memory cell array in response to the data mask signal,
• wherein the data mask signal is generated from an external memory controller based on a plurality of dirty bits associated with the plurality of sector data, respectively.