Memory-bound scheduling

A processing system, comprising:

• a memory comprising computer-executable instructions;
• and
• one or more processors configured to execute the computer-executable instructions and cause the processing system to perform an operation comprising:
• receiving a data flow graph for a process, wherein data flow graph comprises a plurality of nodes and a plurality of edges;
• generating a topological ordering for the data flow graph based at least in part on memory utilization of the process;
• generating a first modified topological ordering by inserting, into the topological ordering, one or more new nodes corresponding to memory access based on a predefined memory capacity;
• allocating units of memory in memory based on the first modified topological ordering;
• and
• generating a second modified topological ordering by rearranging one or more nodes in the first modified topological ordering, wherein the second modified topological ordering enables increased parallel utilization of a plurality of hardware components.

A non-transitory computer-readable medium comprising computer-executable instructions that, when executed by one or more processors of a processing system, cause the processing system to perform an operation comprising:

• receiving a data flow graph for a process, wherein data flow graph comprises a plurality of nodes and a plurality of edges;
• generating a topological ordering for the data flow graph based at least in part on memory utilization of the process;
• generating a first modified topological ordering by inserting, into the topological ordering, one or more new nodes corresponding to memory access based on a predefined memory capacity;
• allocating units of memory in memory based on the first modified topological ordering;
• and
• generating a second modified topological ordering by rearranging one or more nodes in the first modified topological ordering, wherein the second modified topological ordering enables increased parallel utilization of a plurality of hardware components.

A processing system, comprising:

• means for receiving a data flow graph for a process, wherein data flow graph comprises a plurality of nodes and a plurality of edges;
• means for generating a topological ordering for the data flow graph based at least in part on memory utilization of the process;
• means for generating a first modified topological ordering by inserting, into the topological ordering, one or more new nodes corresponding to memory access based on a predefined memory capacity;
• means for allocating units of memory in memory based on the first modified topological ordering;
• and
• means for generating a second modified topological ordering by rearranging one or more nodes in the first modified topological ordering, wherein the second modified topological ordering enables increased parallel utilization of a plurality of hardware components.