Memory devices, carriers for same, and related computing systems and methods

A system, comprising:

• a central processing unit connected to at least one memory device, the at least one memory device comprising a substrate supporting memory chips thereon, the substrate comprising:
• an edge connector at a longitudinal end of the substrate sized, shaped, and configured to provide external electrical connections for the memory devices;
• and
• hook-shaped engagement structures located proximate to, and laterally outward from and longitudinally trailing the edge connector, the engagement structures extending laterally beyond a lateral periphery of the substrate trailing the engagement structures, each engagement structure defining a recess;
• and
• a carrier comprising cutouts shaped, positioned, and configured to receive the hook-shaped engagement structures at least partially therein and posts located within the cutouts, the posts sized, positioned, and configured to be positioned in the recesses of the engagement structures to secure the end of the substrate to the carrier.

A carrier for a memory module, comprising:

• a crossbar extending laterally between mutually parallel sidewalls at one end of the carrier;
• mutually parallel rails defining channels extending longitudinally from proximate the crossbar to proximate an opposing end of the carrier;
• a support structure comprising a post extending vertically between the rails of each sidewall in a channel, the support structure further comprising a cutout in an adjacent sidewall laterally outwardly of the post;
• and
• protrusions proximate the crossbar and extending laterally inwardly from each sidewall, the protrusions extending inwardly of a channel of the respective sidewall of the protrusion, each protrusion having a vertical aperture therethrough positioned for alignment with an aperture of a memory module having lateral edges received within the channel and recesses of laterally outwardly protruding engagement structures of the substrate receiving the posts therein.

A memory module, comprising:

• a substrate bearing multiple memory chips on at least one side thereof;
• the substrate having an interconnect in the form of an edge connector at one end thereof in communication with the multiple memory chips through conductive traces and vias carried by a dielectric material of the substrate;
• engagement structures on opposing edges of the substrate longitudinally trailing the interconnect and extending laterally outwardly therefrom, the engagement structures comprising hooks defining recesses opening to the rear of the engagement structures;
• a portion of the substrate trailing the engagement structures of a lesser width than a width of the substrate at the engagement structures;
• and
• apertures proximate an end of the substrate opposite the interconnect adjacent opposing edges of the substrate.