Semiconductor chip module

A semiconductor chip module including a printed circuit board (PCB) including a first face and a second face facing each other, the semiconductor chip module comprising:

• a first chip on the first face of the PCB, and including a first connection terminal to receive a first signal;
• a second chip on the second placed of the PCB, and including a second connection terminal to receive the first signal;
• and
• a buffer, including a first fin electrically connected to the first connection terminal, and including a second fin electrically connected to the second connection terminal,
• wherein:
• the PCB includes a first wiring structure that provides the first signal from the first connection terminal to the first fin, and a second wiring structure that connects the second connection terminal and the second fin,
• the first wiring structure and the second wiring structure are located symmetrically on the basis of a center line of the buffer from the viewpoint of viewing the PCB in a plane, and
• a mirror function operation is not performed on the first chip and the second chip with respect to each other.

A semiconductor chip module, comprising:

• a printed circuit board (PCB) including a first face and a second face facing each other;
• a buffer on the first face of the PCB;
• a plurality of first memory chips on the first face of the PCB, each first memory chip including a first connection terminal to which a first signal is provided, and performing a first operation in response to the first signal and a first chip selector signal;
• a plurality of second memory chips on the second face of the PCB, each second memory chip including a second connection terminal to which the first signal is provided, and performing the first operation in response to the first signal and the first chip selector signal;
• a plurality of third memory chips on the first face of the PCB, each of the third memory chips including a third connection terminal to which a second signal is provided, and performing a second operation in response to the second signal and a second chip selector signal;
• and
• a plurality of fourth memory chips on the second face of the PCB, each of the fourth memory chips including a fourth connection terminal to which the second signal is provided, and performing the second operation in response to the second signal and the second chip selector signal,
• wherein:
• the first connection terminals of the plurality of first memory chips and the second connection terminals of the plurality of second memory chips receive the first signal from the buffer at the same time, and
• the third connection terminals of the plurality of third memory chips and the fourth connection terminals of the plurality of fourth memory chips receive the second signal from the buffer at the same time.