Fpga based system for decoding pam-3 signals
AssigneeProdigy Technovations Pvt. Ltd.
InventorsPrajeesh PRABHAKAR, Sudarshan SHENOY MULKI, Zakioddin MAHAMMAD
Life of this patent
Estimating the term…
Abstract
An FPGA based system for decoding PAM-3 signals is disclosed, wherein the system comprises a directional coupler for separating 100BASE-T1 and 1000BASE-T1 master and slave signals, DVGAs for amplifying the master and slave signals, ADCs for sampling the amplified signals, and a FPGA module, wherein the FPGA module is configured for decoding the PAM-3 symbols, in real-time, from oversampled ADCs data using fully pipelined Register Transfer Level (RTL) architecture.
Claims20
A system for decoding PAM-3 signals communicating between a master device (D1) and a slave device (D2), the system comprising:
- a directional coupler, connected to a line between the master device (D1) and the slave device (D2), for separating the master and the slave signals;
- a pair of DVGAs configured for amplifying the master and slave signals to a specific voltage range;
- a pair of ADCs configured for converting analog master and slave signals to digital master and slave signals;
- a FPGA module configured for processing both the digital master and slave signals for extracting PAM-3 symbols, wherein the FPGA module (130) comprises:
- ADC interface modules configured for sampling and de-serializing digital master and slave signals;
- DC correction modules configured for employing DC correction to compensate for variations in the signal levels of the de-serialized digital master and slave signals;
- slope and level detection modules configured for decoding PAM-3 levels;
- spike filter modules configured for filtering out spikes in the PAM-3 levels to generate initial PAM-3 levels;
- edge detection modules configured for detecting and storing transitions in the filtered PAM-3 levels;
- a mid-point detection module configured for detecting mid-point of each ‘must transition’;
- first level edge filters and second level edge filters configured for filtering out erroneous transitions in the levels;
- sampling point detection modules configured for calculating sampling point of filtered PAM-3 levels;
- sampling point filtering modules configured for eliminating erroneous sampling points, if any;
- and
- PAM-3 symbol generation module configured for generating PAM-3 symbols from the initial PAM-3 levels using the sampling point.
A method for decoding PAM-3 signals communicating between a master device (D1) and a slave device (D2), the method comprising:
- separating the master and the slave signals communicating between the master device (D1) and the slave device (D2);
- amplifying the master and slave signals to a specific voltage range;
- converting analog master and slave signals to digital master and slave signals;
- and
- processing both the digital master and slave signals for extracting PAM-3 symbols, wherein processing comprises:
- sampling and de-serializing digital master and slave signals;
- employing DC correction to compensate for variations in the signal levels of the de-serialized digital master and slave signals;
- detecting PAM-3 levels from the de-serialized digital master and slave signals;
- filtering out spikes in the PAM-3 levels to generate initial PAM-3 levels;
- generating PAM-3 symbols from the initial PAM-3 levels using a sampling point, wherein the sampling point calculation comprises the steps of:
- detecting all transitions and ‘must transitions’ and registering such transitions of the filtered PAM-3 levels;
- detecting mid-point of each ‘must transition’;
- first and second level filtering to filter out erroneous transitions in the levels;
- calculating sampling point of each registered transitions;
- and
- filtering the sampling points for eliminating erroneous sampling points, if any.
Dependencies are inferred from the claim text.