US 2022/0045682 A1 · LEVEL SHIFTERS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

Abstract

A level shifter includes an input circuit configured to generate and output first and second intermediate signals based on an input signal that transitions between a first voltage level and a second voltage level. The level shifter includes a feed forward circuit configured to receive the first intermediate signal from the input circuit and generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled and to receive the second intermediate signal from the input circuit and generate and output a fourth intermediate signal enabled in a part of a period in which the second intermediate signal is enabled. Moreover, the level shifter includes a level shifting circuit configured to receive the first through fourth intermediate signals and to shift the input signal to an output signal that transitions between a third voltage level and the second voltage level.

Claims21

Dependent claims

A level shifter comprising:

an input circuit configured to generate and output first and second intermediate signals based on an input signal that transitions between a first voltage level and a second voltage level;
a feed forward circuit configured to receive the first intermediate signal from the input circuit and generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled and to receive the second intermediate signal from the input circuit and generate and output a fourth intermediate signal enabled in a part of a period in which the second intermediate signal is enabled;
and
a level shifting circuit configured to receive the first and second intermediate signals from the input circuit and the third and fourth intermediate signals from the feed forward circuit and to shift the input signal to an output signal that transitions between a third voltage level and the second voltage level, wherein the third voltage level is different from the first voltage level.

1 more element

A level shifter comprising:

a first pull-down transistor that is gated based on a first intermediate signal generated by inverting an input signal that transitions between a first voltage level and a second voltage level and is configured to pull down a voltage level of a first node to the second voltage level;
a second pull-down transistor that is gated based on a second intermediate signal generated by inverting the first intermediate signal and is configured to pull down a voltage level of a first output node to the second voltage level;
a first pull-up transistor that is gated based on the voltage level of the first node and is configured to pull up the first output node to a third voltage level greater than the first voltage level;
a first feed forward transistor that is gated based on a third intermediate signal generated by delaying the first intermediate signal and is configured to provide the second intermediate signal to the first node;
and
a second feed forward transistor that is gated based on a fourth intermediate signal generated by delaying the second intermediate signal and is configured to provide the first intermediate signal to the first output node.

3 more elements

Dependencies are inferred from the claim text.

Level shifters and semiconductor devices including the same

Life of this patent

Level shifters and semiconductor devices including the same

Life of this patent

Abstract

Claims21