Input voltage endurance protection architecture

An input voltage endurance protection architecture, wherein the input voltage endurance protection architecture comprises a main operational amplifier, an auxiliary operational amplifier and an input stage voltage endurance protection circuit connected to each other, wherein an input stage of the main operational amplifier comprises a p-channel differential transistor pair with a p-channel tail current resource M1, and wherein a bias current of the main operational amplifier is provided by the current source M1;

• wherein the auxiliary operational amplifier is a single-stage operational that comprises a p-channel transistor pair with Rload to a ground and a p-channel tail current resource M2 connected in series with a degeneration resistor Rbias, and wherein a bias current of the auxiliary operational amplifier is provided by the current source M2;
• and
• wherein the input stage voltage endurance protection circuit comprises a clamping circuit and two N-channel metal oxide semiconductor (NMOS) transistors, wherein gates of the two NMOS transistors are connected to a bias voltage Vbias between the degeneration resistor Rbias and the current source M2, wherein the clamping circuit is connected to sources of the two NMOS transistors, and a drain of one of the two NMOS transistors is connected to an input signal VIP, a source retransmission signal VIP-IN is connected to a gate of a PMOS transistor corresponding to a positive terminal of the main operational amplifier and a gate of a PMOS transistor corresponding to a positive terminal of the auxiliary operational amplifier, and a drain of the other of the two NMOS transistors is connected to an input signal VIN, a source retransmission signal VIN_IN is connected to a gate of the PMOS transistor corresponding to a negative terminal of the main operational amplifier and a gate of the PMOS transistor corresponding to a negative terminal of the auxiliary operational amplifier.