US 2022/0045215 A1Published application

Semiconductor device

AssigneeSocionext Inc.

InventorsHirotaka TAKENO, Atsushi OKAMOTO, Wenzhen WANG

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Abstract

A semiconductor device includes a substrate; first and second fins protruding from the substrate; a first transistor including the first fin; a second transistor above the first transistor; and a first power supply line electrically connected to the first fin through the second fin. The first transistor includes first and second impurity areas in the first fin, and a first gate insulating film on the first fin between the first and second impurity areas. The second transistor includes a first semiconductor area above the first fin, a third impurity area in the first semiconductor area above the first impurity area, a fourth impurity area in the first semiconductor area above the second impurity area, and a second gate insulating film on the first semiconductor area between the third and fourth impurity areas. The first and second transistors have a common gate on the first and second gate insulating films.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate;
a first fin and a second fin protruding from the substrate;
a first transistor including the first fin;
a second transistor above the first transistor;
and
a first power supply line electrically connected to the first fin through the second fin, wherein
the first transistor includes
a first impurity area and a second impurity area formed in the first fin, and
a first gate insulating film formed on the first fin and located between the first impurity area and the second impurity area in a plan view, wherein
the second transistor includes
a first semiconductor area formed above the first fin,
a third impurity area formed in the first semiconductor area and located above the first impurity area,
a fourth impurity area formed in the first semiconductor area and located above the second impurity area, and
a second gate insulating film formed on the first semiconductor area and located between the third impurity area and the fourth impurity area in a plan view, and wherein
the first and second transistors have a common gate formed on the first and second gate insulating films.

12 more elements

A semiconductor device comprising:

a substrate;
a first fin, a second fin, and a third fin, the first fin, the second fin, and the third fin protruding from the substrate;
a first power supply line;
a second power supply line;
a third power supply line;
a switch control circuit disposed between the first power supply line and the second power supply line;
and
a third transistor and a fourth transistor disposed between the second power supply line and the third power supply line, wherein
the first fin has a first conductivity type, wherein
the switch control circuit includes
a first transistor including the first fin, and
a second transistor located above the first transistor and including a first semiconductor area, wherein
the first transistor includes
a first impurity area and a second impurity area formed on the first fin, the first impurity area and the second impurity area each having a second conductivity type differing from the first conductivity type, and
a first gate insulating film formed on the first fin and located between the first impurity area and the second impurity area in a plan view, wherein
the second transistor includes
a third impurity area having the first conductivity type formed in the first semiconductor area and located above the first impurity area,
a fourth impurity area having the first conductivity type formed in the first semiconductor area and located above the second impurity area, and
a second gate insulating film formed on the first semiconductor area and located between the third impurity area and the fourth impurity area in a plan view, wherein
the third transistor includes
a fifth impurity area and a sixth impurity area formed in the third fin, and
a third gate insulating film formed on the third fin and located between the fifth impurity area and the sixth impurity area in a plan view, wherein
the fourth transistor includes
a second semiconductor area formed above the third fin,
a seventh impurity area formed in the second semiconductor area and located above the fifth impurity area,
an eighth impurity area formed in the second semiconductor area and located above the sixth impurity area, and
a fourth gate insulating film formed on the second semiconductor area and located between the seventh impurity area and the eighth impurity area in a plan view, and wherein
the first and second transistors have a common gate formed on the first and second gate insulating films,
the fourth transistor has a common gate formed on the third gate insulating film and the fourth gate insulating film,
a conductivity type of the second fin and a conductivity type of the third fin are identical to each other, and
the second power supply line is electrically connected to the third fin through the second fin.

28 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/508,441Filed 22 Oct 2021
Priority: 25 Apr 2019
Published: 10 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 30/6215
Fin field-effect transistors [FinFET]: having multiple independently-addressable gate electrodes
H10D 84/0193
The components including complementary IGFETs, e.g. CMOS devices: the components including FinFETs
H10D 62/299
Of igfets: having lateral doping variations
H10D 84/0172
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate conductors

Family

Application17/508,441Continuation
US 12,363,940 B2Related patent
US 2022/0045215 A1This patent

From the US filing history. Foreign family members aren’t listed.

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