Semiconductor contact formation

A method of forming a contact surface for a vertically oriented access device, comprising:

• vertically forming a first source/drain region, a channel region on the first source/drain region, and a second source/drain region on the channel region;
• forming a sacrificial etch stop layer including tungsten (W) on the second source/drain region;
• forming a dielectric layer on the sacrificial etch stop layer;
• forming a gate vertically opposing the channel region of the vertically oriented access device, wherein the gate is separated from the channel region by a gate dielectric;
• removing the dielectric layer using a dry etch process to expose the sacrificial etch stop layer;
• and
• removing the sacrificial etch stop layer using a wet etch process to expose the contact surface on the second source/drain region.

A method of forming memory cells having vertically oriented access devices, comprising:

• sequentially depositing a first source/drain region, a channel region, and a second source/drain region to form a vertically oriented structure, wherein the first source/drain region and the second source/drain region are vertically separated by the channel region;
• forming a sacrificial etch stop layer including tungsten (W) on the second source/drain region;
• forming a dielectric layer on the sacrificial etch stop layer;
• forming a gate dielectric over the dielectric layer and the sequentially deposited first source/drain region, channel region, and second source/drain region of the vertically oriented structure;
• forming vertical gates opposing the channel region along side the vertically oriented structure and separated from the channel region by the gate dielectric;
• depositing a second dielectric over the gate dielectric and the vertical gates;
• removing the dielectric layer and the second dielectric using a dry etch process to expose the sacrificial etch stop layer;
• and
• removing the sacrificial etch stop layer using a wet etch chemistry having a high selectivity to the sacrificial etch stop layer relative to the second source/drain region and a compatibility with the channel region to expose a contact surface on the second source/drain region for electrical connection to a storage node.