US 2022/0045191 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a stacked structure having channel formation region layers CH1 and CH2, gate electrode layers G1, G2, and G3 alternately arranged on a base, in which a lowermost layer of the stacked structure is formed with a 1st layer G1 of the gate electrode layers, an uppermost layer of the stacked structure is formed with an Nth (where N≥3) layer G3 of the gate electrode layers, the gate electrode layers each have a first end face, a second end face, a third end face opposing the first end face, and a fourth end face opposing the second end face, the first end face of odd-numbered layers G1, G3 of the gate electrode layers is connected to a first contact portion, and the third end face of an even-numbered layer G2 of the gate electrode layers is connected to a second contact portion.

Claims21

Dependent claims

-7. (canceled)

Dependencies are inferred from the claim text.

Facts

Application

17/409,293Filed 23 Aug 2021

Priority

JP 2018-01347130 Jan 2018

Published

10 Feb 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 62/121
Nanowire, nanosheet or nanotube semiconductor bodies: oriented parallel to substrates
H10D 64/681
Characterised by the insulator, e.g. by the gate insulator: having a compositional variation, e.g. multilayered
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims21