Shield gate trench power device and method for making the same

A method for manufacturing a shield gate trench power device, wherein a gate structure of a device cell region is formed by means of the following steps:

• step 1. providing a semiconductor substrate, wherein a doped epitaxial layer of a first conductivity type is formed on the semiconductor substrate, and a gate trench is formed in the epitaxial layer;
• step 2. forming a shield dielectric layer on the bottom surface and side surface of the gate trench;
• wherein the shield dielectric layer comprises a thermal oxide layer formed by means of a thermal oxidation process and a CVD dielectric layer formed by means of a CVD deposition process, a stack structure of the thermal oxide layer and the CVD dielectric layer increases the thickness of the shield dielectric layer while ensuring the uniformity of the thickness of the shield dielectric layer on the sidewall and bottom of the gate trench, thereby increasing the breakdown voltage of the shield dielectric layer and lowering a breakdown voltage requirement of the epitaxial layer;
• and
• a gap region is formed in a central region of the gate trench, resulting from the shield dielectric layer not fully filling the gate trench;
• step 3. performing polysilicon growth and etch-back processes to fill the gap region of the gate trench with source polysilicon;
• step 4. performing a photolithography process to open a formation region of a top trench, wherein the formation region of the top trench corresponds to a partial region of the shield dielectric layer close to the side surface of the gate trench, anisotropic etching is performed on the shield dielectric layer of the opened region to form the top trench, the entire top trench is located in the thermal oxide layer, a first side surface of the top trench is an exposed side surface of the gate trench, the shield dielectric layer between a second side surface of the top trench and the source polysilicon serves as an inter-polysilicon dielectric layer, in the width direction of the inter-polysilicon dielectric layer, the inter-polysilicon dielectric layer is a stack structure of the CVD dielectric layer and the thermal oxide layer of a partial thickness, the width of the top trench and the width of the inter-polysilicon dielectric layer are defined by means of photolithography at the same time, and the width of the inter-polysilicon dielectric layer is increased to increase Cgs of the device;
• and
• step 5. forming a gate dielectric layer on the first side surface of the top trench and performing polysilicon growth and etch-back processes to fill the top trench where the gate dielectric layer is formed with polysilicon and form a polysilicon gate.