Semiconductor device and method of forming same

A method of forming a semiconductor device, comprising:

• providing a substrate defining a cell region and a non-cell region;
• forming a plurality of trenches in the substrate, the plurality of trenches including a first trench in the cell region and a second trench in the non-cell region;
• forming a lower dielectric layer covering both a bottom and a lower portion of a sidewall of each of the plurality of trenches, wherein forming the lower dielectric layer comprises forming a first lower dielectric layer in the first trench and a second lower dielectric layer in the second trench so that at least an end portion of the second lower dielectric layer is a beak-like portion with a gradually reduced thickness;
• forming an upper dielectric layer covering an upper portion of the sidewall of each of the plurality of trenches, wherein forming the upper dielectric layer comprises forming a sacrificial dielectric layer on the upper portion of the sidewall of the first trench and a second upper dielectric layer on the upper portion of the sidewall of the second trench, the second upper dielectric layer having a thickness smaller than a thickness of the second lower dielectric layer, the second upper dielectric layer smoothly joined to the beak-like portion of the second lower dielectric layer;
• and
• forming electrodes in the plurality of trenches, wherein forming the electrodes comprises:
• forming a shield electrode in a bottom portion of the first trench and a second gate electrode in the second trench, the second gate electrode being an integral structure filling up a bottom portion of the second trench and having a top surface above the shield electrode;
• and successively forming, above the shield electrode, a separation layer, a first upper dielectric layer and a first gate electrode in the first trench, the first upper dielectric layer having a thickness greater than a thickness of the second upper dielectric layer,
• the method further comprising forming a well region, the well region being formed in the substrate beside the first trench and having a lateral overlap with the first gate electrode, the well region further extending to the substrate beside the second trench and having a lateral overlap with the second gate electrode,
• wherein the thickness of the second upper dielectric layer is between 40 Å and 100 Å adjustable according to a concentration of dopant ions in the well region.