Vfet standard cell architecture with improved contact and super via

A cell architecture comprising:

• 1st-type top source/drain (S/D) contact structures respectively formed on top S/D regions of at least two of vertical field-effect transistors (VFETs) constituting a logic circuit, respectively;
• at least one gate contact structure connected to at least one gate connection pattern connecting gates of the two of the VFETs to each other;
• 1st metal patterns extended in a Y-direction and configured to receive one or more input signals of the logic circuit, and transmit out an output signal of the logic circuit;
• and
• 2nd metal patterns extended in an X-direction and provided for internal routing of the logic circuit by connecting at least two of the 1st-type top S/D contact structures to one of the 1st metal patterns to transmit out the output signal,
• wherein the two of the 1st-type top S/D contact structures have a substantially-square shape in a plan view of the cell architecture, and
• wherein the 1st metal patterns are formed at a higher level than the 2nd metal patterns which are formed at a higher level than the 1st-type top S/D contact structures.