Integrated circuit devices including a vertical field-effect transistor and methods of forming the same

An integrated circuit device comprising:

• a first active region and a second active region that are on a substrate and are spaced apart from each other in a first direction, the first active region comprising a first vertical field effect transistor (VFET) and the second active region comprising a second VFET;
• and
• a first isolation layer in the substrate;
• a dummy channel region on the substrate;
• and
• a second isolation layer in the substrate,
• wherein the first isolation layer, the dummy channel region, and the second isolation layer are sequentially arranged in the first direction in a plan view.

A method of forming an integrated circuit device, the method comprising:

• forming first, second and third channel regions on a substrate, wherein the first, second and third channel regions each protrudes from the substrate and are sequentially arranged in a first direction;
• forming first and second bottom source/drain regions in the substrate, wherein the first bottom source/drain region is between the first and second channel regions in a plan view, and the second bottom source/drain region is between the second and third channel regions in the plan view;
• forming first and second isolation layers in the substrate, wherein a portion of the first isolation layer is in the first bottom source/drain region, and a portion of the second isolation layer is in the second bottom source/drain region;
• and then
• forming first and second top source/drain regions on the first and third channel regions, respectively.