Ultra-High Voltage Resistor with Voltage Sense

A method, comprising:

• providing an active region for forming a semiconductor device;
• forming a first charge balance region within the active region;
• forming a drift region within the active region and above the first charge balance region;
• forming a LOCOS region within the active region and extending vertically above a top surface of the active region;
• forming a gate region above the top surface of the active region;
• forming a source region in the active region and laterally disposed from the gate region and the drift region;
• forming a drain region in the active region and laterally disposed from the gate region and the drift region;
• and
• forming a polysilicon resistor above the LOCOS region and substantially laterally aligned with the drift region, the polysilicon resistor having a bottom surface that is offset vertically and physically isolated from the top surface of the LOCOS region.