Display panel, preparing method thereof, and display device

A method for preparing a display panel, comprising steps of:

• provide a substrate layer;
• preparing a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer;
• preparing a buffer layer on the substrate layer, wherein the buffer layer covers the light shielding metal layer and the first electrode plate;
• preparing an active layer and a second electrode plate of the storage capacitor on the buffer layer;
• preparing a gate insulating layer on the buffer layer, wherein the gate insulating layer covers the active layer and the second electrode plate;
• etching the gate insulating layer and the buffer layer to form a first via hole, a second via hole, and a third via hole, respectively;
• conducting a first conductorization of regions of the active layer corresponding to the second via hole and the third via hole;
• preparing a source, a gate, and a drain on the gate insulating layer, wherein the source is connected to the light shielding metal layer through the first via hole;
• the source is connected to one side of the active layer through the second via hole, and the drain is connected to other side of the active layer through the third via hole;
• wherein widths of the source and the drain are both smaller than a width of the active layer,
• wherein a range of a vertical distance between an edge of a projection of the source projected on the active layer and an edge of a projection of the second via hole projected on the active layer is greater than 0 and less than or equal to 2 microns, a range of a vertical distance between an edge of a projection of the drain projected on the active layer and an edge of a projection of the third via hole projected on the active layer is greater than 0 and less than or equal to 2 microns;
• removing regions of the gate insulating layer not covered by the source, the gate, and the drain;
• and
• conducting a second conductorization of the active layer.

A display device comprising a driver chip and a display panel, wherein the display panel comprises:

• a substrate layer;
• a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer;
• a buffer layer covering the light shielding metal layer and the first electrode plate on the substrate layer;
• an active layer and a second electrode plate of the storage capacitor on the buffer layer;
• a gate insulating layer on the buffer layer and the active layer, and
• a source, a gate and a drain on the gate insulating layer;
• wherein the source is connected to the light shielding metal layer through a first via hole;
• a second via hole and a third via hole are defined by the gate insulating layer, the source is connected to one side of the active layer through the second via hole, and the drain is connected to other side of the active layer through the third via hole;
• wherein widths of the source and the drain are both smaller than a width of the active layer, a range of a vertical distance between an edge of a projection of the source projected on the active layer and an edge of a projection of the second via hole projected on the active layer is greater than 0 and less than or equal to 2 microns, and a range of a vertical distance between an edge of a projection of the drain projected on the active layer and an edge of a projection of the third via hole projected on the active layer is greater than 0 and less than or equal to 2 microns.